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学者姓名:李景虎
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This paper presents a low-power low-dropout regulator integrated with a bandgap reference (LDO-BGR) system that achieves exceptional low-frequency power-supply rejection (PSR). The proposed architecture employs three novel feedback loops, enabling functional reuse of a single error amplifier for both the shared-feedback-loop BGR (SF-BGR) and the LDO. This shared-loop approach enhances PSR while maintaining voltage headroom. A dynamic response technique combined with power gating improves load-transient performance without increasing the quiescent current. The capacitor-less LDO operates from a 2.5 V supply while regulating the output to 2.2 V, demonstrating a room-temperature quiescent current of 370 nA and supporting a maximum load current of 50 mA. Post layout simulations show worst-case PSR of-101 dB at 1 Hz and-47.8 dB at 1 kHz across the specified load range, with a transient figure-of-merit (FoM1) of 0.219 mV.
Keyword :
Dynamic response technique Dynamic response technique LDO-BGR system LDO-BGR system PSR PSR Shared feedback loop BGR (SF-BGR) Shared feedback loop BGR (SF-BGR)
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| GB/T 7714 | Xie, Jin , Chen, Qibin , Li, Jinghu et al. A 370-nA capacitor-less LDO-BGR system for PSR enhancement via shared feedback loops [J]. | MICROELECTRONICS JOURNAL , 2026 , 167 . |
| MLA | Xie, Jin et al. "A 370-nA capacitor-less LDO-BGR system for PSR enhancement via shared feedback loops" . | MICROELECTRONICS JOURNAL 167 (2026) . |
| APA | Xie, Jin , Chen, Qibin , Li, Jinghu , Pan, Xingxing , Luo, Zhicong , Zhang, Jianwei . A 370-nA capacitor-less LDO-BGR system for PSR enhancement via shared feedback loops . | MICROELECTRONICS JOURNAL , 2026 , 167 . |
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The combination of electroencephalography (EEG) signals with peripheral physiological signals (PPS) for emotion recognition has garnered increasing attention due to their objectivity and rich information content. However, the heterogeneity and correlations of multimodal physiological signals remain significant challenges in multimodal emotion recognition. In addition, effectively extracting spatiotemporal features from these physiological signals is crucial for accurate emotion recognition. To address these issues, we propose a multimodal emotion recognition framework based on intra-and inter-modal supervised contrastive learning (IAECL), using EEG and PPS signals as inputs. Specifically, IAECL employs modality-specific encoders to mitigate heterogeneity. In addition, a dual-level supervised contrastive learning strategy is introduced: intra-modal contrastive learning enhances the feature compactness within each modality, and inter-modal contrastive learning strengthens cross-modal correlations. To better extract complex spatiotemporal features from EEG, we further a novel EEG encoder that integrates graph-based modeling, spatial-temporal convolution, and multi-head attention. This design effectively captures inter-channel dependencies and enhances local-global feature interactions to improve EEG feature representation. Extensive experiments on the publicly available DEAP and DREAMER datasets demonstrated the superior performance of IAECL, which achieved state-of-the-art results in both within-subject and mixed-subject emotion classification tasks. Visualization analyses further revealed that IAECL effectively aligns multimodal features to enhance inter-modal correlations, offering a novel solution to the challenges of multi-modal emotion recognition. We also analyzed the optimal combination of other physiological signals (e.g., electromyography or temperature recording signals) with EEG for multimodal emotion recognition.
Keyword :
EEG EEG Emotion recognition Emotion recognition Multimodal physiological signal Multimodal physiological signal Spatiotemporal features Spatiotemporal features Supervised contrastive learning Supervised contrastive learning
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| GB/T 7714 | Zhao, Rongyue , Ma, Tianyuan , Li, Wangsen et al. EEG-based multimodal emotion recognition framework with supervised contrastive learning and spatial-temporal convolutional attention network [J]. | DIGITAL SIGNAL PROCESSING , 2026 , 168 . |
| MLA | Zhao, Rongyue et al. "EEG-based multimodal emotion recognition framework with supervised contrastive learning and spatial-temporal convolutional attention network" . | DIGITAL SIGNAL PROCESSING 168 (2026) . |
| APA | Zhao, Rongyue , Ma, Tianyuan , Li, Wangsen , Li, Yihua , Li, Jinghu , Huang, Dong et al. EEG-based multimodal emotion recognition framework with supervised contrastive learning and spatial-temporal convolutional attention network . | DIGITAL SIGNAL PROCESSING , 2026 , 168 . |
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Addressing the challenges of variable target morphology, small critical regions, and complex background interference in eggplant picking point detection within complex agricultural scenarios, this study proposes MDAD-YOLO (Multi-dimensional Attention and DySample YOLO), a detection model improved based on the YOLOv10n-pose framework. First, the model's cross-dimensional perception ability for fruits and picking points is enhanced by integrating the collaborative mechanism of regional receptive field attention with channel-space joint attention. Next, within the Neck structure, coordinate attention is incorporated to optimize the spatial localization accuracy of fine-grained features, enhancing sensitivity to minute regions such as the fruit stem apex. Additionally, dynamic pixel reorganization is applied to enhance feature map reconstruction details, addressing the detail loss caused by traditional interpolation methods. Finally, cascading adaptive fine-grained channel attention with position-sensitive attention enables multi-level modeling of channel dependencies and collaborative spatial context enhancement. Through a seven-tier validation framework, the model's effectiveness, robustness, and generalizability have been comprehensively demonstrated. Experimental results show that the model achieves 93.6% mAP@50 for object detection, 94.7% mAP@50 and 92.1% mAP for keypoints detection, and an average pixel Euclidean distance error of 19.41 on the self-built eggplant dataset, outperforming YOLOv12 and other high-performance models. Additionally, cross-crop experiments on the pepper dataset showed a 2.1% and 2.7% improvement in mAP for object and picking point detection, respectively, compared to the baseline model, confirming its cross-crop robustness. This study reveals the synergistic enhancement of dynamic upsampling and attention mechanisms in agricultural object detection, providing new insights for lightweight model design in complex scenarios.
Keyword :
Dynamic upsampling Dynamic upsampling MDAD-YOLO MDAD-YOLO Multi-dimensional attention mechanism Multi-dimensional attention mechanism Object detection Object detection Picking point detection Picking point detection
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| GB/T 7714 | Huang, Yikun , Li, Gang , Li, Jinghu et al. Accurate localization of fruit targets and picking points with multi-dimensional attention and dynamic upsampling [J]. | COMPUTERS AND ELECTRONICS IN AGRICULTURE , 2026 , 240 . |
| MLA | Huang, Yikun et al. "Accurate localization of fruit targets and picking points with multi-dimensional attention and dynamic upsampling" . | COMPUTERS AND ELECTRONICS IN AGRICULTURE 240 (2026) . |
| APA | Huang, Yikun , Li, Gang , Li, Jinghu , Chen, Hao , Lin, Hefei , Yang, Changcai et al. Accurate localization of fruit targets and picking points with multi-dimensional attention and dynamic upsampling . | COMPUTERS AND ELECTRONICS IN AGRICULTURE , 2026 , 240 . |
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This paper presents a low-power low-dropout regulator integrated with a bandgap reference (LDO-BGR) system that achieves exceptional low-frequency power-supply rejection (PSR). The proposed architecture employs three novel feedback loops, enabling functional reuse of a single error amplifier for both the shared-feedback-loop BGR (SF-BGR) and the LDO. This shared-loop approach enhances PSR while maintaining voltage headroom. A dynamic response technique combined with power gating improves load-transient performance without increasing the quiescent current. The capacitor-less LDO operates from a 2.5~V supply while regulating the output to 2.2~V, demonstrating a room-temperature quiescent current of 370~nA and supporting a maximum load current of 50~mA. Measurements show worst-case PSR of $-101$~dB at 1~Hz and $-48$~dB at 1~kHz across the specified load range, with a transient figure-of-merit (FoM) of 0.219~mV. © 2025, The Authors. All rights reserved.
Keyword :
Dynamic response Dynamic response Dynamics Dynamics Feedback Feedback Power quality Power quality Transients Transients Voltage regulators Voltage regulators
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| GB/T 7714 | Xie, Jin , Chen, Qibin , Li, Jinghu et al. A 370‑nA Capacitor-less LDO–BGR System for PSR Enhancement via Shared Feedback Loops [J]. | SSRN , 2025 . |
| MLA | Xie, Jin et al. "A 370‑nA Capacitor-less LDO–BGR System for PSR Enhancement via Shared Feedback Loops" . | SSRN (2025) . |
| APA | Xie, Jin , Chen, Qibin , Li, Jinghu , Pan, Xingxing , Luo, Zhicong , Zhang, Jianwei . A 370‑nA Capacitor-less LDO–BGR System for PSR Enhancement via Shared Feedback Loops . | SSRN , 2025 . |
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A low-area and low-temperature-coefficient (TC) bandgap reference (BGR) circuit using curvature compensation technology is presented. Comparing with traditional BGR with multiple BJT, four MOSFETs biased in their weak-inversion regions can produce a proportionalto-absolute-temperature (PTAT) voltage without consuming a great active area. In addition, a curvature compensation circuit was adopted to reduce the drift of temperature. The proposed BGR circuit has been implemented using a 0.18um technology, occupying an area of 0.01 mm2.Simulation results demonstrate that the BGR achieves average TC of 7.86ppm/degrees C from -40 degrees C to 125 degrees C at 3.3 V and the line regulation (LR) of 0.048%/V between 2.7 and 3.6 V supply voltage, respectively.
Keyword :
and bandgap reference voltage and bandgap reference voltage curvature compensation curvature compensation low-area low-area Sub-threshold Sub-threshold
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| GB/T 7714 | Yan, Zhenjie , Zhang, Binhan , Yang, Rui et al. A 1.2-V compact Bandgap Reference with Curvature Compensation technology [J]. | IEICE ELECTRONICS EXPRESS , 2025 , 22 (7) . |
| MLA | Yan, Zhenjie et al. "A 1.2-V compact Bandgap Reference with Curvature Compensation technology" . | IEICE ELECTRONICS EXPRESS 22 . 7 (2025) . |
| APA | Yan, Zhenjie , Zhang, Binhan , Yang, Rui , Zheng, Yi , Li, Jinghu , Luo, Zhicong et al. A 1.2-V compact Bandgap Reference with Curvature Compensation technology . | IEICE ELECTRONICS EXPRESS , 2025 , 22 (7) . |
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In this paper, we present a novel enhanced recycling folded cascode (ERFC) operational transconductance amplifier (OTA), which exhibits high efficiency and a fast transient response under weak inversion. Our innovative combination of adaptive biasing with nested local feedback (ABNLF) effectively enhances the input transconductance and slew rate (SR), thus improving the transient response. By incorporating coupling capacitors at the output stage, we achieve a stable operating region with large signal responses. Both the traditional RFC OTA and the proposed ERFC OTA were designed in a 0.18 mu m CMOS process, operating at a power supply of 1.8 V, with quiescent currents of 8 mu A and 10.4 mu A, respectively. Post-layout simulations reveal a remarkable enhancement in the proposed ERFC OTA over the traditional RFC OTA, with the SR and gain-bandwidth (GBW) surging by 120- and 5.95-fold, respectively. This advancement boosts the efficiency of the traditional RFC OTA and provides an impressive figure of merit (FoM) of 130.04 (V/mu s)pF/mu A.
Keyword :
adaptive biasing adaptive biasing enhanced recycling folded cascode (ERFC) enhanced recycling folded cascode (ERFC) high efficiency high efficiency nested local feedback technique nested local feedback technique transient response transient response
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| GB/T 7714 | Wu, Chunkai , Cai, Peng , Li, Jinghu et al. Power-Efficient Recycling Folded Cascode Operational Transconductance Amplifier Based on Nested Local Feedback and Adaptive Biasing [J]. | SENSORS , 2025 , 25 (8) . |
| MLA | Wu, Chunkai et al. "Power-Efficient Recycling Folded Cascode Operational Transconductance Amplifier Based on Nested Local Feedback and Adaptive Biasing" . | SENSORS 25 . 8 (2025) . |
| APA | Wu, Chunkai , Cai, Peng , Li, Jinghu , Xie, Jin , Luo, Zhicong . Power-Efficient Recycling Folded Cascode Operational Transconductance Amplifier Based on Nested Local Feedback and Adaptive Biasing . | SENSORS , 2025 , 25 (8) . |
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This article presents a fully integrated, capacitor-less analog low-dropout regulator (LDO) employing a time-voltage hybrid domain control architecture to achieve a wide operating range and fast transient response. The hybrid-domain approach featuring a hybrid triple-loop control scheme is introduced, a time-domain feedback loop, together with two voltage-domain feedback loops, cooperatively achieves wide band high power-supply rejection (PSR). This approach also removes the clock-frequency recovery limitation of conventional time-domain LDOs, thereby improving load transient response. An improved charge-pump circuit with an additional current branch reduces current mismatch and improves DC regulation. This work is designed in 180-nm CMOS and supports an input range of 0.8-1.8 V and an output range of 0.7-1.7 V. The quiescent current is 27 mu A when the input voltage is 0.8 V. Simulated PSR is-70 dB at 1 kHz and better than-40 dB at 1 MHz. Under a 19.9 mA load step with a 1 ns edge time, the overshoot recovery time is less than 47 ns.
Keyword :
Fast transient response Fast transient response Hybrid triple-loop control Hybrid triple-loop control Time-voltage hybrid domain Time-voltage hybrid domain Wide operating range Wide operating range
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| GB/T 7714 | Xie, Jin , Chen, Qibin , Li, Jinghu et al. A triple-loop hybrid-domain LDO with wide operating range and 47 ns recovery in 180 nm CMOS [J]. | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 204 . |
| MLA | Xie, Jin et al. "A triple-loop hybrid-domain LDO with wide operating range and 47 ns recovery in 180 nm CMOS" . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 204 (2025) . |
| APA | Xie, Jin , Chen, Qibin , Li, Jinghu , Luo, Zhicong , Zhang, Jianwei . A triple-loop hybrid-domain LDO with wide operating range and 47 ns recovery in 180 nm CMOS . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 204 . |
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This paper presents a high-efficiency dual-mode off-time controlled buck converter with a novel seamless and fast mode transition scheme. The proposed seamless fast mode transition (SFMT) technique employs a mode selector consisting of a voltage detector (VD) and ripple-to-digital conversion circuit (RDC), solving the prolonged frequency transition problem in conventional mode-switching methods. Additionally, the introduced dynamic sleep clock management adaptively disables idle circuits based on duty cycle variations, achieving high efficiency across wide load ranges. Implemented in 0.18- mu s technology, the converter occupies 0.5525 mm(2) while operating from a 2.5-3.6 V input to deliver 1.2 V output. Measurement results demonstrate $93.7 % peak efficiency at 0.4 A load and 80.5 % high light-load efficiency at 1 mA. The design achieves < 192 mV output voltage spike under 0.08 - 1.5 A load transients (2.32 A/mu s slew rate) with 28-mu s recovery time, while maintaining low output ripple. Compared with reported designs, the proposed buck converter achieves an outstanding figure-of-merit (FoM(1)) of 7.26 mu s/(A(2)/mm(2)).
Keyword :
buck converter buck converter Buck converters Buck converters Circuits Circuits Clocks Clocks Detectors Detectors Dual-mode Dual-mode dynamic sleep clock management dynamic sleep clock management light-load efficiency light-load efficiency Pulse width modulation Pulse width modulation seamless and fast mode transition seamless and fast mode transition Switches Switches Switching frequency Switching frequency Transient analysis Transient analysis Voltage control Voltage control Voltage-controlled oscillators Voltage-controlled oscillators
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| GB/T 7714 | Xie, Jin , Chen, Qibin , Zhang, Jianwei et al. A High Efficiency Dual Mode Buck Converter With a Novel Seamless and Fast Transition Scheme [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 . |
| MLA | Xie, Jin et al. "A High Efficiency Dual Mode Buck Converter With a Novel Seamless and Fast Transition Scheme" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2025) . |
| APA | Xie, Jin , Chen, Qibin , Zhang, Jianwei , Chen, Yun , Chen, Jinhui , Li, Jinghu et al. A High Efficiency Dual Mode Buck Converter With a Novel Seamless and Fast Transition Scheme . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 . |
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A cross-connected NPN bandgap reference (BGR) circuit with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is proposed by using curvature-compensated and pre-regulation techniques. Compared with the traditional BGR, it does not require an operational amplifier to clamp the voltage, but uses the voltage feedback of the cross-connected NPN to clamp the voltage, making the structure simpler and eliminating the need to design an operational amplifier. Additionally, by subtracting two nearly identical positive-temperature-coefficient currents, the circuit generates a new current with enhanced curvature, which is then used as a compensating current to reduce the overall temperature coefficient. This compensating current is subsequently scaled by different gain factors to accommodate process-corner variations and serve as a trimming current. Meanwhile, the pre-regulation circuit is respectively adopted to improve PSRR. The proposed BGR circuit is implemented in a 180-nm process, boasting a minimal active area of 0.016 mm2. Simulation results show that the BGR has a best TC of 4.13 ppm/degrees C from-40 degrees C to 125 degrees C at 3.3 V, a PSRR of-122 dB at low frequencies, and a linear regulation (LR) of 0.0027 mV/V within the supply voltage range of 3.0 V to 3.6 V.
Keyword :
Bandgap reference voltage Bandgap reference voltage Cross-connected NPN Cross-connected NPN Curvature-compensated Curvature-compensated Pre-regulation Pre-regulation
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| GB/T 7714 | Zheng, Yi , Yan, Zhenjie , Yang, Rui et al. A-122 dB PSRR curvature-compensated bandgap reference with cross-connected NPN [J]. | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 202 . |
| MLA | Zheng, Yi et al. "A-122 dB PSRR curvature-compensated bandgap reference with cross-connected NPN" . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 202 (2025) . |
| APA | Zheng, Yi , Yan, Zhenjie , Yang, Rui , Zhang, Binhan , Luo, Zhicong , Li, Jinghu . A-122 dB PSRR curvature-compensated bandgap reference with cross-connected NPN . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 202 . |
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A low-power, low-temperature-coefficient (TC), and compact bandgap reference (BGR) circuit is presented.Comparing with conventional multi-BJT structures, the proposed design employs a differential-pair voltage generator to produce proportional-to-absolute-temperature (PTAT) voltage without a large active area consumption.By compensating the nonlinear component of VBE (base-emitter voltage), the TC is effectively reduced.The proposed BGR circuit has been implemented using a 0.18i.zm technology, occupying an area of 0.027 mm2. Simulation results demonstrate that at 1.2 V output, the BGR achieves an average TC of 2.83 ppm/degrees C over the temperature range from-40 degrees C to 125 degrees C, with a power consumption of merely 0.33 i.zW.
Keyword :
Bandgap reference Bandgap reference low-power low-power low TC and VBE nonlinear component low TC and VBE nonlinear component
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| GB/T 7714 | Zhang, Binhan , Pan, Xingxing , Li, Jinghu et al. A 1.2-V 2.83-p p m /°C 0.33-μW Bandgap Reference With Nonlinear Compensation of VBE [J]. | IEICE ELECTRONICS EXPRESS , 2025 . |
| MLA | Zhang, Binhan et al. "A 1.2-V 2.83-p p m /°C 0.33-μW Bandgap Reference With Nonlinear Compensation of VBE" . | IEICE ELECTRONICS EXPRESS (2025) . |
| APA | Zhang, Binhan , Pan, Xingxing , Li, Jinghu , Luo, Zhicong , Ye, Dapeng . A 1.2-V 2.83-p p m /°C 0.33-μW Bandgap Reference With Nonlinear Compensation of VBE . | IEICE ELECTRONICS EXPRESS , 2025 . |
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