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学者姓名：罗志聪
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Abstract ：
This paper presents a low-power low-dropout regulator integrated with a bandgap reference (LDO-BGR) system that achieves exceptional low-frequency power-supply rejection (PSR). The proposed architecture employs three novel feedback loops, enabling functional reuse of a single error amplifier for both the shared-feedback-loop BGR (SF-BGR) and the LDO. This shared-loop approach enhances PSR while maintaining voltage headroom. A dynamic response technique combined with power gating improves load-transient performance without increasing the quiescent current. The capacitor-less LDO operates from a 2.5 V supply while regulating the output to 2.2 V, demonstrating a room-temperature quiescent current of 370 nA and supporting a maximum load current of 50 mA. Post layout simulations show worst-case PSR of-101 dB at 1 Hz and-47.8 dB at 1 kHz across the specified load range, with a transient figure-of-merit (FoM1) of 0.219 mV.
Keyword ：
Dynamic response technique Dynamic response technique LDO-BGR system LDO-BGR system PSR PSR Shared feedback loop BGR (SF-BGR) Shared feedback loop BGR (SF-BGR)
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| GB/T 7714 | Xie, Jin , Chen, Qibin , Li, Jinghu et al. A 370-nA capacitor-less LDO-BGR system for PSR enhancement via shared feedback loops [J]. | MICROELECTRONICS JOURNAL , 2026 , 167 . |
| MLA | Xie, Jin et al. "A 370-nA capacitor-less LDO-BGR system for PSR enhancement via shared feedback loops" . | MICROELECTRONICS JOURNAL 167 (2026) . |
| APA | Xie, Jin , Chen, Qibin , Li, Jinghu , Pan, Xingxing , Luo, Zhicong , Zhang, Jianwei . A 370-nA capacitor-less LDO-BGR system for PSR enhancement via shared feedback loops . | MICROELECTRONICS JOURNAL , 2026 , 167 . |
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本发明涉及显示控制技术领域，具体为显示器自监控方法、系统以及显示器，包括以下步骤：收集光强度数据与预设标准对比分类环境光为低光、强光或反射光，判断实时色温与标准色温差值是否超阈值，超出则调整色温与亮度，逐帧提取像素RGB通道比例并生成色域分布图，记录修复指令时间特征并统计色温调整趋势，生成背光梯度补偿模式。本发明中，通过实时监测显示器周围的光强度，并与预设的光照条件进行对比，自动分类环境光情况，使得显示器能够针对不同光照环境调整色温和亮度，通过逐帧分析显示帧中红、绿、蓝三通道的覆盖面积，及时调整显示器的背光驱动，提高显示器在变化光照条件下的适应能力和长期稳定性，为用户提供更加优化的视觉体验。
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| GB/T 7714 | 陈杰睿 , 修新田 , 罗志聪 . 显示器自监控方法、系统以及显示器 : CN202510611929.6[P]. | 2025-05-13 . |
| MLA | 陈杰睿 et al. "显示器自监控方法、系统以及显示器" : CN202510611929.6. | 2025-05-13 . |
| APA | 陈杰睿 , 修新田 , 罗志聪 . 显示器自监控方法、系统以及显示器 : CN202510611929.6. | 2025-05-13 . |
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Abstract ：
This paper presents a low-power low-dropout regulator integrated with a bandgap reference (LDO-BGR) system that achieves exceptional low-frequency power-supply rejection (PSR). The proposed architecture employs three novel feedback loops, enabling functional reuse of a single error amplifier for both the shared-feedback-loop BGR (SF-BGR) and the LDO. This shared-loop approach enhances PSR while maintaining voltage headroom. A dynamic response technique combined with power gating improves load-transient performance without increasing the quiescent current. The capacitor-less LDO operates from a 2.5~V supply while regulating the output to 2.2~V, demonstrating a room-temperature quiescent current of 370~nA and supporting a maximum load current of 50~mA. Measurements show worst-case PSR of $-101$~dB at 1~Hz and $-48$~dB at 1~kHz across the specified load range, with a transient figure-of-merit (FoM) of 0.219~mV. © 2025, The Authors. All rights reserved.
Keyword ：
Dynamic response Dynamic response Dynamics Dynamics Feedback Feedback Power quality Power quality Transients Transients Voltage regulators Voltage regulators
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| GB/T 7714 | Xie, Jin , Chen, Qibin , Li, Jinghu et al. A 370‑nA Capacitor-less LDO–BGR System for PSR Enhancement via Shared Feedback Loops [J]. | SSRN , 2025 . |
| MLA | Xie, Jin et al. "A 370‑nA Capacitor-less LDO–BGR System for PSR Enhancement via Shared Feedback Loops" . | SSRN (2025) . |
| APA | Xie, Jin , Chen, Qibin , Li, Jinghu , Pan, Xingxing , Luo, Zhicong , Zhang, Jianwei . A 370‑nA Capacitor-less LDO–BGR System for PSR Enhancement via Shared Feedback Loops . | SSRN , 2025 . |
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A low-area and low-temperature-coefficient (TC) bandgap reference (BGR) circuit using curvature compensation technology is presented. Comparing with traditional BGR with multiple BJT, four MOSFETs biased in their weak-inversion regions can produce a proportionalto-absolute-temperature (PTAT) voltage without consuming a great active area. In addition, a curvature compensation circuit was adopted to reduce the drift of temperature. The proposed BGR circuit has been implemented using a 0.18um technology, occupying an area of 0.01 mm2.Simulation results demonstrate that the BGR achieves average TC of 7.86ppm/degrees C from -40 degrees C to 125 degrees C at 3.3 V and the line regulation (LR) of 0.048%/V between 2.7 and 3.6 V supply voltage, respectively.
Keyword ：
and bandgap reference voltage and bandgap reference voltage curvature compensation curvature compensation low-area low-area Sub-threshold Sub-threshold
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| GB/T 7714 | Yan, Zhenjie , Zhang, Binhan , Yang, Rui et al. A 1.2-V compact Bandgap Reference with Curvature Compensation technology [J]. | IEICE ELECTRONICS EXPRESS , 2025 , 22 (7) . |
| MLA | Yan, Zhenjie et al. "A 1.2-V compact Bandgap Reference with Curvature Compensation technology" . | IEICE ELECTRONICS EXPRESS 22 . 7 (2025) . |
| APA | Yan, Zhenjie , Zhang, Binhan , Yang, Rui , Zheng, Yi , Li, Jinghu , Luo, Zhicong et al. A 1.2-V compact Bandgap Reference with Curvature Compensation technology . | IEICE ELECTRONICS EXPRESS , 2025 , 22 (7) . |
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In this paper, we present a novel enhanced recycling folded cascode (ERFC) operational transconductance amplifier (OTA), which exhibits high efficiency and a fast transient response under weak inversion. Our innovative combination of adaptive biasing with nested local feedback (ABNLF) effectively enhances the input transconductance and slew rate (SR), thus improving the transient response. By incorporating coupling capacitors at the output stage, we achieve a stable operating region with large signal responses. Both the traditional RFC OTA and the proposed ERFC OTA were designed in a 0.18 mu m CMOS process, operating at a power supply of 1.8 V, with quiescent currents of 8 mu A and 10.4 mu A, respectively. Post-layout simulations reveal a remarkable enhancement in the proposed ERFC OTA over the traditional RFC OTA, with the SR and gain-bandwidth (GBW) surging by 120- and 5.95-fold, respectively. This advancement boosts the efficiency of the traditional RFC OTA and provides an impressive figure of merit (FoM) of 130.04 (V/mu s)pF/mu A.
Keyword ：
adaptive biasing adaptive biasing enhanced recycling folded cascode (ERFC) enhanced recycling folded cascode (ERFC) high efficiency high efficiency nested local feedback technique nested local feedback technique transient response transient response
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| GB/T 7714 | Wu, Chunkai , Cai, Peng , Li, Jinghu et al. Power-Efficient Recycling Folded Cascode Operational Transconductance Amplifier Based on Nested Local Feedback and Adaptive Biasing [J]. | SENSORS , 2025 , 25 (8) . |
| MLA | Wu, Chunkai et al. "Power-Efficient Recycling Folded Cascode Operational Transconductance Amplifier Based on Nested Local Feedback and Adaptive Biasing" . | SENSORS 25 . 8 (2025) . |
| APA | Wu, Chunkai , Cai, Peng , Li, Jinghu , Xie, Jin , Luo, Zhicong . Power-Efficient Recycling Folded Cascode Operational Transconductance Amplifier Based on Nested Local Feedback and Adaptive Biasing . | SENSORS , 2025 , 25 (8) . |
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This article presents a fully integrated, capacitor-less analog low-dropout regulator (LDO) employing a time-voltage hybrid domain control architecture to achieve a wide operating range and fast transient response. The hybrid-domain approach featuring a hybrid triple-loop control scheme is introduced, a time-domain feedback loop, together with two voltage-domain feedback loops, cooperatively achieves wide band high power-supply rejection (PSR). This approach also removes the clock-frequency recovery limitation of conventional time-domain LDOs, thereby improving load transient response. An improved charge-pump circuit with an additional current branch reduces current mismatch and improves DC regulation. This work is designed in 180-nm CMOS and supports an input range of 0.8-1.8 V and an output range of 0.7-1.7 V. The quiescent current is 27 mu A when the input voltage is 0.8 V. Simulated PSR is-70 dB at 1 kHz and better than-40 dB at 1 MHz. Under a 19.9 mA load step with a 1 ns edge time, the overshoot recovery time is less than 47 ns.
Keyword ：
Fast transient response Fast transient response Hybrid triple-loop control Hybrid triple-loop control Time-voltage hybrid domain Time-voltage hybrid domain Wide operating range Wide operating range
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| GB/T 7714 | Xie, Jin , Chen, Qibin , Li, Jinghu et al. A triple-loop hybrid-domain LDO with wide operating range and 47 ns recovery in 180 nm CMOS [J]. | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 204 . |
| MLA | Xie, Jin et al. "A triple-loop hybrid-domain LDO with wide operating range and 47 ns recovery in 180 nm CMOS" . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 204 (2025) . |
| APA | Xie, Jin , Chen, Qibin , Li, Jinghu , Luo, Zhicong , Zhang, Jianwei . A triple-loop hybrid-domain LDO with wide operating range and 47 ns recovery in 180 nm CMOS . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 204 . |
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This paper presents a high-efficiency dual-mode off-time controlled buck converter with a novel seamless and fast mode transition scheme. The proposed seamless fast mode transition (SFMT) technique employs a mode selector consisting of a voltage detector (VD) and ripple-to-digital conversion circuit (RDC), solving the prolonged frequency transition problem in conventional mode-switching methods. Additionally, the introduced dynamic sleep clock management adaptively disables idle circuits based on duty cycle variations, achieving high efficiency across wide load ranges. Implemented in 0.18- mu s technology, the converter occupies 0.5525 mm(2) while operating from a 2.5-3.6 V input to deliver 1.2 V output. Measurement results demonstrate $93.7 % peak efficiency at 0.4 A load and 80.5 % high light-load efficiency at 1 mA. The design achieves < 192 mV output voltage spike under 0.08 - 1.5 A load transients (2.32 A/mu s slew rate) with 28-mu s recovery time, while maintaining low output ripple. Compared with reported designs, the proposed buck converter achieves an outstanding figure-of-merit (FoM(1)) of 7.26 mu s/(A(2)/mm(2)).
Keyword ：
buck converter buck converter Buck converters Buck converters Circuits Circuits Clocks Clocks Detectors Detectors Dual-mode Dual-mode dynamic sleep clock management dynamic sleep clock management light-load efficiency light-load efficiency Pulse width modulation Pulse width modulation seamless and fast mode transition seamless and fast mode transition Switches Switches Switching frequency Switching frequency Transient analysis Transient analysis Voltage control Voltage control Voltage-controlled oscillators Voltage-controlled oscillators
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| GB/T 7714 | Xie, Jin , Chen, Qibin , Zhang, Jianwei et al. A High Efficiency Dual Mode Buck Converter With a Novel Seamless and Fast Transition Scheme [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 . |
| MLA | Xie, Jin et al. "A High Efficiency Dual Mode Buck Converter With a Novel Seamless and Fast Transition Scheme" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2025) . |
| APA | Xie, Jin , Chen, Qibin , Zhang, Jianwei , Chen, Yun , Chen, Jinhui , Li, Jinghu et al. A High Efficiency Dual Mode Buck Converter With a Novel Seamless and Fast Transition Scheme . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 . |
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A cross-connected NPN bandgap reference (BGR) circuit with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is proposed by using curvature-compensated and pre-regulation techniques. Compared with the traditional BGR, it does not require an operational amplifier to clamp the voltage, but uses the voltage feedback of the cross-connected NPN to clamp the voltage, making the structure simpler and eliminating the need to design an operational amplifier. Additionally, by subtracting two nearly identical positive-temperature-coefficient currents, the circuit generates a new current with enhanced curvature, which is then used as a compensating current to reduce the overall temperature coefficient. This compensating current is subsequently scaled by different gain factors to accommodate process-corner variations and serve as a trimming current. Meanwhile, the pre-regulation circuit is respectively adopted to improve PSRR. The proposed BGR circuit is implemented in a 180-nm process, boasting a minimal active area of 0.016 mm2. Simulation results show that the BGR has a best TC of 4.13 ppm/degrees C from-40 degrees C to 125 degrees C at 3.3 V, a PSRR of-122 dB at low frequencies, and a linear regulation (LR) of 0.0027 mV/V within the supply voltage range of 3.0 V to 3.6 V.
Keyword ：
Bandgap reference voltage Bandgap reference voltage Cross-connected NPN Cross-connected NPN Curvature-compensated Curvature-compensated Pre-regulation Pre-regulation
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| GB/T 7714 | Zheng, Yi , Yan, Zhenjie , Yang, Rui et al. A-122 dB PSRR curvature-compensated bandgap reference with cross-connected NPN [J]. | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 202 . |
| MLA | Zheng, Yi et al. "A-122 dB PSRR curvature-compensated bandgap reference with cross-connected NPN" . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 202 (2025) . |
| APA | Zheng, Yi , Yan, Zhenjie , Yang, Rui , Zhang, Binhan , Luo, Zhicong , Li, Jinghu . A-122 dB PSRR curvature-compensated bandgap reference with cross-connected NPN . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 202 . |
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Abstract ：
A low-power, low-temperature-coefficient (TC), and compact bandgap reference (BGR) circuit is presented.Comparing with conventional multi-BJT structures, the proposed design employs a differential-pair voltage generator to produce proportional-to-absolute-temperature (PTAT) voltage without a large active area consumption.By compensating the nonlinear component of VBE (base-emitter voltage), the TC is effectively reduced.The proposed BGR circuit has been implemented using a 0.18i.zm technology, occupying an area of 0.027 mm2. Simulation results demonstrate that at 1.2 V output, the BGR achieves an average TC of 2.83 ppm/degrees C over the temperature range from-40 degrees C to 125 degrees C, with a power consumption of merely 0.33 i.zW.
Keyword ：
Bandgap reference Bandgap reference low-power low-power low TC and VBE nonlinear component low TC and VBE nonlinear component
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| GB/T 7714 | Zhang, Binhan , Pan, Xingxing , Li, Jinghu et al. A 1.2-V 2.83-p p m /°C 0.33-μW Bandgap Reference With Nonlinear Compensation of VBE [J]. | IEICE ELECTRONICS EXPRESS , 2025 . |
| MLA | Zhang, Binhan et al. "A 1.2-V 2.83-p p m /°C 0.33-μW Bandgap Reference With Nonlinear Compensation of VBE" . | IEICE ELECTRONICS EXPRESS (2025) . |
| APA | Zhang, Binhan , Pan, Xingxing , Li, Jinghu , Luo, Zhicong , Ye, Dapeng . A 1.2-V 2.83-p p m /°C 0.33-μW Bandgap Reference With Nonlinear Compensation of VBE . | IEICE ELECTRONICS EXPRESS , 2025 . |
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This paper presents a CMOS voltage reference circuit designed to achieve high power supply rejection ratio (PSRR) across a wide frequency range while maintaining a low temperature coefficient (TC). The circuit uses voltage self-regulating technology to mitigate the impact of power supply ripple on the output voltage. Additionally, a compact MOSFET-based low-pass filter is integrated into the output stage to further enhance high-frequency PSRR performance. The temperature coefficient (TC) of the reference voltage is optimized using an improved design of stacked diode-connected MOS transistors (SDMTs) with different current biasing. The circuit was designed using a 65-nm process. Post-simulation results indicate that the reference voltage output is 415 mV, with an average TC of 10.42 ppm/degrees C across a temperature range of-40 degrees C to 125 degrees C. Within the supply voltage range of 0.8-1.32 V, the line sensitivity (LS) of the reference voltage is about 0.104 mV/V. It is worth highlighting that the PSRR reaches-128.95 dB at 10 kHz and maintains-63.05 dB at 50 MHz.
Keyword ：
CMOS voltage reference CMOS voltage reference Filter Filter High PSRR High PSRR Low temperature coefficient Low temperature coefficient Subthreshold Subthreshold
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| GB/T 7714 | Zheng, Baiqi , Chen, Qibin , Qiu, Hangfang et al. A 10.42 ppm/°C CMOS voltage reference with high PSRR [J]. | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 198 . |
| MLA | Zheng, Baiqi et al. "A 10.42 ppm/°C CMOS voltage reference with high PSRR" . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 198 (2025) . |
| APA | Zheng, Baiqi , Chen, Qibin , Qiu, Hangfang , He, Lili , Li, Jinghu , Luo, Zhicong . A 10.42 ppm/°C CMOS voltage reference with high PSRR . | AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS , 2025 , 198 . |
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